This actually ties into another issue I pondered recently (https://udongein.xyz/objects/6ce0987e-e953-4d12-ace2-5990d3ddf422).
This makes it so that we're often stuck with chips that have deep flaws in their design and which microcode patches are often unable to really fix. FPGAs would fix that.
And then there's the timing/power correlation analysis countermeasures that FPGAs would enable and which conventional CPUs mostly can't.
LisPi
npub132…qgzqx
2025-04-03 02:34:13 UTC
in reply to nevent1q…e5ja
Author Public Key
npub1326y4p8mw4l750yc8e52n0xguvcl5j0dn88ul5r2gjva2sh2ay7qjqgzqxPublished at
2025-04-03 02:34:13 UTCEvent JSON
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