niconiconi on Nostr: #TIL Why does GCC generate useless "mv" instructions from a register to itself in ...
#TIL Why does GCC generate useless "mv" instructions from a register to itself in RISC-V assembly? Is it some super advanced tuning for out-of-order CPUs or something? No. Just an unimplemented optimization...
https://sourceware.org/bugzilla/show_bug.cgi?id=31175Published at
2024-07-22 12:56:39Event JSON
{
"id": "105f2afaedcafee878a7f145251dc7c8fb1919f82dfc9e415ad6f7da9b6f299b",
"pubkey": "26fdcfc5f6ff27a9926ef372554241c70b1042094ec7749aa301091e34d17aa0",
"created_at": 1721652999,
"kind": 1,
"tags": [
[
"t",
"til"
],
[
"emoji",
"woozypad",
"https://mk.absturztau.be/files/3478c83e-8c07-40a0-9ad1-0276c1482ad3"
],
[
"proxy",
"https://mk.absturztau.be/notes/9w0k21ko000l01e4",
"activitypub"
]
],
"content": "#TIL Why does GCC generate useless \"mv\" instructions from a register to itself in RISC-V assembly? Is it some super advanced tuning for out-of-order CPUs or something? No. Just an unimplemented optimization... :woozypad: https://sourceware.org/bugzilla/show_bug.cgi?id=31175",
"sig": "d438bc170830f121af8ea7f5c6fd17611b0f2d9a26542f426ec0532655c8789cf5a0a896a38c545e7e05df6b1bbc085e1008817d924fd02d1057b6f44d5d08c1"
}