🇺🇦 haxadecimal 🚫👑 on Nostr: As I understand it, CMOS latchup is caused by triggering parasitic SCR structures ...

As I understand it, CMOS latchup is caused by triggering parasitic SCR structures (PNPN), and that standard CMOS process design rules make it extremely unlikely to be internally triggered under normal operating conditions. An SEU can inject enough energy to trigger a parasitic SCR.
SOS and SOI CMOS fabrication eliminate the parasitic SCRs, but are typically only used for mil/aerospace due to expense.