Arguably you can construct a usable topology by making every write into a read-modify-write cycle... But ugh, it's such an odd layout, why??
I assume the answer to why is another one of the FPGA blocks you can use is a DSP block that can do 18x18 multiplication. And I presume 18b is still a useful width for some DSP-ish things that FPGAs are made to do? Presumably the reason is no longer parity with electromechanical calculators.
Dave Anderson
npub1mt…xwant
2024-08-17 06:03:57 UTC
in reply to nevent1q…78am
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2024-08-17 06:03:57 UTCEvent JSON
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