Wanda on Nostr: the columns are FPGA families; they are: 2k -> XC2000 3k -> XC3000*/XC3100* 4k -> ...

the columns are FPGA families; they are:

2k -> XC2000
3k -> XC3000*/XC3100*
4k -> XC4000
4ka -> XC4000A
4kh -> XC4000H
4ke -> XC4000E/XC4000L/Spartan
4kx -> XC4000EX/XC4000XL
4kxla -> XC4000XLA
4kxv -> XC4000XV
sxl -> Spartan XL
5k -> XC5200
virtex -> Virtex / Virtex E / Spartan-II / Spartan-II E
2v -> Virtex II / Virtex II Pro / Virtex II Pro X
3s -> Spartan 3
fc -> FPGAcore
3se -> Spartan 3E
3sa -> Spartan 3A
3sda -> Spartan 3A DSP
6s -> Spartan 6
4v -> Virtex 4
5v -> Virtex 5
6v -> Virtex 6
7v -> Virtex 7 / Kintex 7 / Artix 7 / Spartan 7 / Zynq 7000
us -> Kintex Ultrascale / Virtex Ultrascale
us+ -> Spartan Ultrascale+ / Artix Ultrascale+ / Kintex Ultrascale+ / Virtex Ultrascale+ / Zynq Ultrascale MPSoC / Zynq Ultrascale RFSoC
versal -> we shall not speak of this thing

the rows are:

DB: have extracted a routing / chip geometry database
BS:FRAME: can parse bitstream framing
BS:GEOM: understand bitstream geometry and can cut them to tiles
BS:CRC: understand bitstream CRC algorithm
BS:COMPRESS: understand compressed bitstreams
BS:ENCRYPT: understand encrypted bitstreams
BS:ECC: understand per-frame ECC algorithm (to be done last for reasons)
BS:PCRC: understand post-configuration CRC algorithm (to be done last for reasons)
INT:MAIN: general interconnect (aka the main FPGA fabric)
INT:INTF: interconnect interface (programmable delays and fancy loopback features that are part of interconnect's DFT)
INT:CLK: clock interconnect
CLB: configurable logic block
BRAM: block RAM
DSP: hard multiplier / DSP blocks
URAM: UltraRAM
LAGUNA: fancy cross-die crossing thingies
IO:IOB: I/O buffers (physical layer of I/O, such as drive strength control)
IO:IOI: I/O interface (flops, gearboxes, etc)
IO:BANK: I/O per-bank stuff (DCI, LVDS bias generators, ...)
IO:HRIOB: I/O buffers, high-range version (aka 3.3V capable)
IO:HRBANK I/O per-bank stuff, high-range version
IO:MCB: memory controller block
IO:FIFO: virtex 7 fancy dedicated I/O hard FIFO logic
IO:PHY: dedicated memory controller PHY stuff
IO:HDIO: high-density I/O (the ones that have 3.3V support but no fancy gearboxes on newer devices)
CLKBUF:*: various kinds of clock buffers
CLK:*: various clock management primitives
CFG:*: various global stuff and misc config options, aka. the config center
GT:*: multi-gigabit transceivers of various genders
RFDAC/RFADC: fancy expensive high-speed ADC/DAC form Zynq RFSoC
HARD:*: various hard IP blocks

status is T/I/D/O for TODO/inprogress/done/out-of-scope; for most of the rows, an item is considered done when I have extracted the positions and rough meanings for all bitstream bits and put them in a database