Dave Anderson on Nostr: I think as it happens in my current sketch the lopsided operation latencies wouldn't ...

I think as it happens in my current sketch the lopsided operation latencies wouldn't matter, because all the writes would happen on port A, where the FPGA just needs to run faster than the system bus. On port B where the video pipeline is pulling data, everything is read-only and remains single cycle. Just trying to decide if I care or not, really :)