Anyway, having a huge pipeline is only going to annihilate your Fmax. Instead have a “programmable ALU” with 128/256 bit path, RAM to store registers and operation microcode in ROM-ish blocks
It’ll still be faster than CPU, this is how most hardware accelerators for ECDSA work
semisol
npub122…cgrkj
2026-05-03 15:55:54 UTC
in reply to nevent1q…kvkn
Author Public Key
npub12262qa4uhw7u8gdwlgmntqtv7aye8vdcmvszkqwgs0zchel6mz7s6cgrkjPublished at
2026-05-03 15:55:54 UTCEvent JSON
{
"id": "38db265163e2dead10512fbf7f23116d674f03d27ea46786950eafd3abbb9e15",
"pubkey": "52b4a076bcbbbdc3a1aefa3735816cf74993b1b8db202b01c883c58be7fad8bd",
"created_at": 1777823754,
"kind": 1,
"tags": [
[
"e",
"96c2fd4ffbefb80d94e8c13680d54940356650af9914fec9be28f7cd66ce32c1",
"wss://relay.damus.io",
"root",
"4c5d5379a066339c88f6e101e3edb1fbaee4ede3eea35ffc6f1c664b3a4383ee"
],
[
"e",
"e6cd8723f57c2d5b4b84374bf366c101b86c033716c111baceeeaa7c11267c74",
"wss://nos.lol",
"reply",
"52b4a076bcbbbdc3a1aefa3735816cf74993b1b8db202b01c883c58be7fad8bd"
],
[
"p",
"4c5d5379a066339c88f6e101e3edb1fbaee4ede3eea35ffc6f1c664b3a4383ee"
]
],
"content": "Anyway, having a huge pipeline is only going to annihilate your Fmax. Instead have a “programmable ALU” with 128/256 bit path, RAM to store registers and operation microcode in ROM-ish blocks\n\nIt’ll still be faster than CPU, this is how most hardware accelerators for ECDSA work",
"sig": "abdbab5267529539bf99b9fcb940949bfa6862eee01fffa39fa4ee069f13cdd36d1059f645e6f781c08c29a3a0b1f13d2baf64068a4e330c98da4d47db66b92e"
}