Sorry, I just took one of your two arguments away.
1. The source code Verilog/VHDL/SystemC is as a work sufficiently similar to software to be copyrightable.
The other I took away before:
2. The transformation process is similar to compiling software (and I know how to write compilers and synthesis tools) that if one of these transformation processes is agreed to retain copyright, the other must be, too.
The limitations here means I must take one argument at a time.