npub1nv0qcmgdhv0nmetyh24evlaazpahlhfh9uz4rr7vwmuls2wy9pys7hskkw (npub1nv0…skkw) anime graf mays 🛰️🪐 (npub108z…dkr5) pistolero (npub1ch8…sw60) the ECC in ddr5 is basically signal correction, it's not the same ECC as you would have in ECC DDR RAM. Generally (I haven't done enough reading into DDR5), there's a whole chip that does nothing but keep parity information.
If DDR5 RAM chips are failing, they fail like you're used to.